FIG. 1 (Prior Art) is a circuit diagram of a conventional circuit for converting an analog signal into a digital signal. The circuit consists of a front end device 10, a comparator 12, a recovery data generator 14 and a resampling clock generator 16. The front end device 10 is used to amplify and low-pass filter the front end signal S.sub.input so as to obtain an input analog signal V.sub.in which includes reduced high-frequency noise, and to provide an impedance match. The comparator 12 is used to compare the input analog signal V.sub.in with a threshold voltage V.sub.t, which is approximately the midvalue of logic 1 and logic 0, so as to obtain a corresponding output binary signal V.sub.out representing logic values of the input analog signal V.sub.in. The recovery data generator 14 is used to receive the output binary signal V.sub.out as the binary output D.sub.out of the front end signal S.sub.input. The resampling clock generator 16, which may be provided by a phase-locked loop (PLL), is used to output a resampling clock CK according to the output binary signal V.sub.out for next-stage systems.
FIG. 2 (Prior Art) depicts the waveforms of each node of the circuit shown in FIG. 1. In this case, a periodic sine wave is used to represent the front end signal S.sub.input. A mid-value of a positive voltage source and a negative voltage source is used to define the threshold voltage V.sub.t for convenience (when the positive voltage source is V.sub.DD and the negative voltage source is 0, the threshold voltage is chosen as V.sub.DD /2). The sine wave is depicted in FIG. 2 with three possible values of the threshold voltage: V.sub.t1, V.sub.t2 and V.sub.t3.
When the threshold voltage is at the value V.sub.t1 shown in FIG. 2, which is approximately equal to the DC component of the front end signal S.sub.input, the duty cycle (the ratio of the input analog signal V.sub.in read as logic one to the input analog signal read as either logic one or logic zero) of the input analog signal V.sub.in is approximately 50%. The resampling clock generator 16 always generates a resampling clock CK1 using a phase-locked loop (having a frequency twice that of the front end signal S.sub.input and having a duty cycle of 50%). Therefore, with the threshold so selected, the output digital signal D.sub.out1, 101010 in this case and not shown in FIG. 2, can be obtained by sampling the output digital signal V.sub.out1, from the comparator 12 at the correct timing.
However, a misreading may possibly occur in the circuit described above. This is due to an analog signal offset introduced when the signal S.sub.input is input to the front end device 10. When the threshold voltage V.sub.t remains at the mid-value of the positive and negative voltage sources, the threshold voltage V.sub.t can be lower (see, e.g., V.sub.t2) or higher (see, e.g. V.sub.t3) than the DC component of the front end signal S.sub.input entering the front end device 10 (i.e. the front end signal S.sub.input is shifted higher or lower) and the duty cycle of the input analog signal V.sub.in can consequently be greater than 75% or less than 25%. Since the resampling clock generator 16 still generates a resampling clock (CK2, CK3) having a duty cycle of 50%, a misreading therefore occurs when sampling the input analog signal V.sub.in using the negative edges of the resampling clock CK2, CK3. The output binary signal D.sub.out2, D.sub.out3 (not shown) in this case may be all logic one or all logic zero.
Many inventions in this area of technology are concerned with improving the front end device 10 to reduce the analog signal offset and the misreading caused thereby. However, it is difficult to improve the front end device 10 by analog circuit design since a low voltage-level and high-sensitivity circuit may be subject to interference by a variation in any component of the circuit. Consequently, most improvements are not suitable for batch process manufacturing.